Romanian Journal of Information Science and Technology (ROMJIST)

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ROMJIST is a publication of Romanian Academy,
Section for Information Science and Technology

Editor – in – Chief:
Radu-Emil Precup

Honorary Co-Editors-in-Chief:
Horia-Nicolai Teodorescu
Gheorghe Stefan

Secretariate (office):
Adriana Apostol
Adress for correspondence: romjist@nano-link.net (after 1st of January, 2019)

Founding Editor-in-Chief
(until 10th of February, 2021):
Dan Dascalu

Editing of the printed version: Mihaela Marian (Publishing House of the Romanian Academy, Bucharest)

Technical editor
of the on-line version:
Lucian Milea (University POLITEHNICA of Bucharest)

Sponsor:
• National Institute for R & D
in Microtechnologies
(IMT Bucharest), www.imt.ro

ROMJIST Volume 28, No. 2, 2025, pp. 185-196, DOI: 10.59277/ROMJIST.2025.2.06
 

Murad ALABDULLAH, Natalia SEOANE, Antonio GARCIA-LOUREIRO, Karol KALNA
Impact of Scaling and Interface Roughness on Drain Current in Nanosheet and Nanowire FETs: A 3D Monte Carlo Analysis

ABSTRACT: A 3D finite-element Monte Carlo simulation toolbox, incorporating Schrödinger equation-based quantum corrections, is employed to analyze the performance of nanosheet (NS) and nanowire (NW) field-effect transistors (FETs), which emerged as promising candidates for sub-3 nm CMOS technology. The study investigates the impact of scaling gate length and oxide thickness, increase in source/drain doping concentration, and interface roughness on these architectures. Results indicate that NS-FETs achieve higher ON currents than NW FETs. However, scaling the gate length below 12 nm reduces the drain current in both devices with a ⟨110⟩ channel orientation – by 9.4% in NS and 7.7% in NW. To understand this decline, valley population and average electron velocity are examined. Scaling dielectric thickness has a smaller effect on NW-FETs with 12 nm and 10 nm gate lengths compared to NS-FETs. In contrast, changes in maximum doping concentration have a greater impact on NW than NS, due to better electrostatic control and increased carrier injection resulting from reduced source/drain resistance. A back-scattering effect is observed in the 12 nm and 10 nm gate length devices, particularly NWs, but it can be mitigated by increasing doping concentration. Interface roughness significantly degrades drain current (IDD), with a more pronounced impact on NWs. Their smaller surface-to-volume ratio and stronger quantum confinement increase sensitivity to roughness variations, as most carriers are closer to the surface, leading to more scattering events. On the contrary, NSs, despite interface roughness, benefit from a larger conductive cross-section, maintaining higher effective mobility in the device channel.

KEYWORDS: Gate-All-Around; Monte Carlo; nanosheet; nanowire; scaling

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