ROMJIST Volume 25, No. 1, 2022, pp. 47-57
Sarada MUSALA, P. Vijaya LAKSHMI, K. Kumar LOKESH, Avireni SRINIVASULU, Cristian RAVARIU Implementation of Semi-Static and Differential Null Convention Logic Gates Using CNTFET Technology
ABSTRACT: This paper aims to implement NULL Convention Logic gates using CNTFET technology. NCL is a clockless technique to solve timing problems, and CNTFET is a low-power technology in comparison to the others. Hence high performance and efficient circuits with low power and low delay can be obtained by combining the two techniques. In terms of power, latency, power delay product, and transistor count, various asynchronous NULL Convention Logic (NCL) gates semi static, and differential have been implemented using CNTFET technology and is compared with the existing CNTFET based NCL static gates, based on the observations gates suitable for adder design is identified. Differential NCL gates have low power and better PDP when compared to both static and semi-static NCL gates. The number of transistors used for differential NCL logic gates are minimum equivalent to semi-static logic and are lesser than static NCL gates. All the simulations are carried out using CNTFET 32nm technology in cadence virtuoso tool and the results obtained prove that the CNTFET based differential logic gates are efficient enough in terms of delay, power consumption and PDP.KEYWORDS: NCL Logic, logic gates, CNTFET, low power, low delayRead full text (pdf)